It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip. As the size of DRAMs is decreased, the capacity of the capacitor used in the DRAM is correspondingly decreased.
A memory cell of DRAM typically consists of a storage capacitor and an access transistor. With the advent of large-scale integrated DRAM devices, the size of the devices has gotten smaller and smaller such that the available area for a single memory cell has become very small. This causes a reduction in the capacitor's area, resulting in the reduction of the cell's capacitance.
One method for increasing capacitance area involves forming hemispherical grain (HSG) polysilicon on amorphous polysilicon and increasing capacitor height. However, increasing capacitor height requires an increase in the thickness of the amorphous polysilicon layer which requires an increased deposition time for the amorphous polysilicon layer. An increased deposition time causes crystallization of the amorphous polysilicon. Crystallization of the amorphous polysilicon inhibits silicon migration resulting in poor HSG formation atop the amorphous polysilicon, thereby decreasing area gain.
Furthermore, the step height difference of the conventional stacked capacitor creates difficulty in planarization. The conventional stacked capacitor has a bottom storage node height (or amorphous polysilicon layer thickness) of 6000 to 9000 angstroms and a polysilicon top plate thickness of 500 to 1500 angstroms. The step height difference between the cell and the peripheral layers renders planarization difficult.
Therefore, there is a need for an improved method of manufacturing a stacked capacitor that reduces crystallization of the amorphous polysilicon and that allows improved planarization.